`blargCPU` documentation

`blargCPU` CPU

The blargCPU CPU operates on 16-bit words at a time. Many processors have the capability of addressing 8-bit bytes independently; a blargCPU system does not.

Opcode format

A blargCPU opcode is a 16-bit word, like everything else. It is formatted as the following table might suggest:

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
instruction				predicate			set flags	target register				source register

legend: n/c is "don't care" or "not connected"

Instruction list

blargCPU has 13 currently-defined instructions, and they are:

0000: mov reg, lit16
Loads the literal constant that follows the instruction into the register specified in bits 7-4 of the opcode (i.e., the target register). The instruction moval r0, 0x1234 might then be assembled as 0E00 1234, or as binary, 0000 1110 0000 0000, 0001 0010 0011 0100.
0001: ldr reg, [reg]
0010: sto [reg], reg
0011: mov treg, sreg
0100: add treg, sreg
0101: sub treg, sreg
0110: and treg, sreg
0111: not treg, sreg
1000: push spreg, sreg
1001: pop spreg, treg
1010: call spreg, sreg
1011: shr treg, sreg
1100: shl treg, sreg

Canonical memory map

Joshua's implementation of a blargCPU system has the following map:

bottom of memory
0x0000	Read-only memory
...
0x3FFF
0x4000	Console output device
0x4100 0x4103	Video framebuffer
0x8000	RAM
...
0xFFFF

blargCPU documentation

blargCPU CPU

Opcode format

Instruction list

Canonical memory map

`blargCPU` documentation

`blargCPU` CPU